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a ver l ogic t echnologies , i nc . tel : 1 408 361 - 0400 e - mail: sales@averlogic.com url: www.averlogic.com november 28 , 2001 AL440B data sheets version 1.0
AL440B AL440B november 28 , 2001 2 amendments 11 - 28 - 01 AL440B version 1.0 release data sheets.
al44 0b AL440B november 28 , 2001 3 AL440B 4mbits fifo field memory contents: 1.0 description ________________________________ ________________________________ _ 4 2.0 features ________________________________ ________________________________ ____ 4 3.0 applications ________________________________ ________________________________ _ 4 4.0 ordering information ________________________________ _________________________ 4 5.0 pin - out diagram ________________________________ _____________________________ 5 6.0 block diagram ________________________________ ______________________________ 5 7.0 pin definition and description ________________________________ __________________ 6 8.0 register definition ________________________________ ___________________________ 8 8.1 register set ________________________________ ________________________________ ____________ 8 9.0 multiple devices bus expansion and cascading ________________________________ ___ 9 10.0 serial bus interface ________________________________ _________________________ 9 11.0 memory operation ________________________________ _________________________ 11 11.1 power - on - reset & initialization ________________________________ __________________________ 11 11.2 wrst, rrst reset operation ________________________________ ___________________________ 11 11.3 control signals polarity select ________________________________ ___________________________ 11 11.4 fifo write operation ________________________________ ________________________________ __ 12 11.5 fifo read operation ________________________________ ________________________________ ___ 12 11.6 irdy, ordy flags ________________________________ ________________________________ ____ 13 11.7 wi ndow write register programming ________________________________ _____________________ 14 11.8 window read register programming ________________________________ ______________________ 17 12.0 electrical characteristics ________________________________ ____________________ 19 12.1 absolute maximum ratings ________________________________ _____________________________ 19 12.2 recommended operating conditions ________________________________ ______________________ 19 12.3 dc characteristics ________________________________ ________________________________ _____ 19 12.4 ac characteristics ________________________________ ________________________________ _____ 20 13.0 timing diagrams ________________________________ __________________________ 22 14.0 mech anical drawing ? 44 pin plastic tsop (ii) ______________________________ 30 15.0 application notes ________________________________ __________________________ 32 15.1 chip global reset recommend circuit ________________________________ _____________________ 32 15.2 the AL440B reference schematic ________________________________ ________________________ 32
al44 0b AL440B november 28 , 2001 4 1.0 description the AL440B 4mbits (512k x 8 - bit) fifo memory provides completely independent 8bit input and output ports that can operate at a maximum speed of 80 mhz. the built - in address and pointer control circuits provide a very easy - to - use memory interface that greatly reduces design time and effort. manufactured using state - of - the - art embedded high density memory cell array, the AL440B uses high performance process technologies with extended controller functions (write mask, re ad skip.. etc.), allowing easy operation of non - linearity and regional read/write fifo for pip, digital tv, security system and video camera applications. the status flags can be used to indicate fullness/emptiness of the fifo and also allow m ultiple casc ading AL440Bs to expand the storage depth or provide a longer delay, which cannot be achieved with only a single device. expanding AL440B data bus width is also possible by using multiple AL440B chips in parallel. to get better design flexibility, the po larities of the AL440B control signals are selectable. the read and write control signals, such as read/write enable, input/output enable.., can be either active low or high by pulling /plrty signal to high or low respectively. in AL440B, window data wri te/read and data mirroring functions can offer better control assistance in the application design. the built - in registers set can be easily programmed via serial bus (i2c like control bus) to perform various useful functions such as multi - freeze, p - in - p in the digital tv, vcr, and video camera application. available as a 44 - pin tsop (ii), the small footprint allows product designers to keep real estate to a minimum. 2.0 features 4mbits (512k x 8 bits) organization fifo independent 8bit read/writ e port operations (different read/write data rates acceptable) maximum read/write cycle time: 80mhz and 40mhz (2 speed grades) input enable (write mask) / output enable (data skipping) control window read/write with mirroring capable selectable control si gnal polarity input ready / output ready flags direct cascade connection self refresh 3.3v 10% power supply standard 44 - pin tsop (ii) package 3.0 applications multimedia systems video capture or editing systems for ntsc/pal or svga resolution securi ty systems scan rate converters pip (picture - in - picture) video display tbc (time base correction) frame synchronizer digital video camera hard disk cache memory buffer for communication systems * * 8 8 0 0 m m h h z z h h i i g g h h - - s s p p e e e e d d v v e e r r s s i i o o n n dtv/hdtv video stream buffer 4. 0 ordering information the AL440B has two speed grades, AL440B - 24 and AL440B - 12, which can operate at frequencies of 40mhz and 80mhz respectively. both speed grades are powered by 3.3v and are available in a 44 - pin standard tsop - ii package.
al44 0b AL440B november 28 , 2001 5 part numbe r package power supply status AL440B - 24 (40mhz) 44 - pin plastic tsop(ii) +3.3v 10% sample dec., 2001 AL440B - 12 (80mhz) 44 - pin plastic tsop(ii) +3.3v 10% sample dec.., 2001 5.0 pin - out diagram the AL440B pin - out diagram is following. di1 AL440B-12/24 tsop (ii) pinout diagram (top view) averlogic AL440B-xx xxxxx xxxx 1 lot number date code speed 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 di2 di3 vdd di4 di5 di6 di7 we ie di0 gnd wck wrst irdy /plrty test avdd nc nc nc agnd /sdaen scl sda gnd /reset nc vdd ordy rrst rck gnd oe re do7 do6 do5 do4 vdd do3 do2 do1 do0 6.0 block diagram timing generator & arbiter control registers memory control output control iutput control 512kx8 memory cell array oe rck rrst re wck wrst we AL440B block diagram di[7:0] write data register read data register scl & sda internal bus ie /sdaen irdy ordy internal bus control bus address bus to all modules to all modules do[7:0] timing & logic control refresh counter input buffer output buffer /plrty /reset
al44 0b AL440B november 28 , 2001 6 the internal structure of the AL440B consists of an input/output buffers, write data registers, read data registers and main 512k x8 memory cell array and the state - of - the - art logic design that ta kes care of addressing and controlling the read/write data. 7.0 pin definition and description the pin definitions and descriptions are as follows: write bus signals pin name pin number i/o type description di[7:0] 9,8,7,6,4,3,2, 1 i the di pins input 8 bits of data. data input is synchronized with the wck clock. data is acquired at the rising edge of wck clock. we 10 i we is an input signal that controls the 8bit input data write and write pointer operation. ie 11 i ie is an input signal that contr ols the enabling/ disabling of the 8bit data input pins. the internal write address pointer is always incremented at rising edge of wck by enabling we regardless of the ie level. wck 13 i wck is the write clock input pin. the write data input is synchro nized with this clock. wrst 14 i the wrst is a reset input signal that resets the write address pointer to 0. irdy 15 o irdy is a status output flag that reports the fifo space availability. *note: for the polarity definition of all write control sig nals (we, ie, wrst and irdy), please refer to /plrty pin definition and ?memory operation? section for details. read bus signals pin name pin number i/o type description do[7:0] 36,37,38,39, 41,42,43,44 o the do pins output 8bit of data. data output is synchronized with the rck clock. data is output at the rising edge of the rck clock. re 35 i re is an input signal that controls the 8bit output data read and read pointer operation. oe 34 i oe is an input signal that controls the enabling/ disabling of the 8bit data output pins. the internal read address pointer is always incremented at rising edge of rck by enabling re regardless of the oe level. rck 32 i rck is the read clock input pin. the read data
al44 0b AL440B november 28 , 2001 7 output is synchronized with this clock. rrst 31 i the rrst is a reset input signal that resets the read address pointer to 0. ordy 30 o ordy is a status output flag that reports the fifo data availability. *note: for the polarity definition of all read control signals (re, oe, rrst and ordy), ple ase refer to /plrty pin definition and ?memory operation? section for details. serial port bus signals pin name pin number i/o type description sda 25 i/o sda carries the serial bus read/write data bits. the sda data bit is valid when the scl is high a fter start up sequence. scl 24 i scl supplies the serial bus clock signal to fifo. the serial data bit is valid when the scl is high after start up sequence. /sdaen 23 i /sdaen controls the enabling/disabling of serial bus interface. when /sdaen is hig h, the serial interface is disabled and sda pin is high impedance. when /sdaen is low, the serial interface is enabled and data can be written to or read from the fifo registers. power/ground signals pin name pin number i/o type description v dd 5, 29, 4 0 - 3.3v 10%. gnd 12, 26, 33 - ground. av dd 18 - dedicated power pin for the internal oscillator. 3.3v 10%. agnd 22 - dedicated ground pin for the internal oscillator. miscellaneous signals pin name pin number i/o type description /reset 27 i the global reset pin /reset will automatically initialize chip logic. for the recommended circuit for the global reset signal, please refer to the application notes.
al44 0b AL440B november 28 , 2001 8 /plrty 16 i select active polarity of the control signals including we, re, wrst, rrs t, ie, oe, irdy and ordy totally 8 signals /plrty = v dd , active low. /plrty = gnd, active high. note: during memory operation, the pin must be permanently connected to vdd or gnd. if /plrty level is changed during memory operation, memory data is not guar anteed. test 17 i for testing purpose only. no connect or connect to ground. nc 19,20,21,28 - no connect or connect to ground 8.0 register definition there are some built - in registers in the AL440B that allows performing some optional functions such a s window read/write access. these registers can be programmed via serial bus (sda, scl and /sdaen). the serial bus interface protocol is illustrated in ?serial bus interface? chapter. the serial bus control software code or tool is available at averlogi c technologies, inc. upon request. 8.1 register set address register r/w description 00h companyid r company id (46h) 02h wstart_l r/w window write starting address (low byte) 03h wstart_h r/w window write starting address (high byte) 04h wxsize_l r/w window write horizontal size (low byte) 05h wxsize_h r/w window write horizontal size (high byte) 06h wstride_l r/w window write strike size (low byte) 2?s complement (for y - mirror) 07h wstride_h r/w window write strike size (high byte) 2?s compl ement (for y - mirror) 08h wysize_l r/w window write vertical size (low byte) 09h wysize_h r/w window write vertical size (high byte) 0ah wwctrl r/w window write control register [7]: enable window write function [6]: x mirror [5]: freeze 0bh rstart_l r/w window read starting address (low byte) 0ch rstart_h r/w window read starting address (high byte) 0dh rxsize_l r/w window read horizontal size (low byte) 0eh rxsize_h r/w window read horizontal size (high byte) 0fh rstride_l r/w window read strike size (low byte) 10h rstride_h r/w window read strike size (high byte) 11h rysize_l r/w window read vertical size (low byte)
al44 0b AL440B november 28 , 2001 9 12h rysize_h r/w window read vertical size (high byte) 13h rwctrl r/w window read control register [7]: enable window read fun ction 9.0 multiple devices bus expansion and cascading the AL440B fifo memory can be applied to very wide range of media applications. a parallel connect or cascade of multiple AL440B fifos provides fifo bus width or memory depth expansion for some a pplications; eg. accommodating hdtv resolution.. etc. AL440B expanding & cascading 8-bit output di[7:0] al440 irdy we wck do[7:0] ordy re rck di[7:0] al440 irdy we wck do[7:0] ordy re rck 8-bit output di[7:0] al440 irdy we wck do[7:0] ordy re rck di[7:0] al440 irdy we wck do[7:0] ordy re rck fifo empty write enable write clock fifo empty fifo full read enable read clock fifo full (1) logic block: "or" gate if /plty = high, "and" gate if /plty = high (2) always enabled : tie to low if /plty = high, tie to high if /plty = low (1) (1) (1) (1) rrst wrst rrst rrst rrst wrst wrst wrst write reset read reset 8-bit output 8-bit input ie oe input enable ie ie ie oe oe oe 8-bit input output enable 8-bit output (2) (2) (2) (2) 10.0 serial bus interface the serial bus interface consists of the scl (serial clock), sda (serial data) and /sdaen (serial interface enable) signals. there are pull up circuit internally for both scl and sda pins. when /sdaen is high, the serial bus interface is disabled and both scl and sda pins are pulled high. when /sdaen is low, the serial bus interface is enabled and data can be written into or read from the al440 b register set. for both read and write, each byte is transferred msb first and lsb last, and the sda data bit is valid when the scl is pulled high. the serial bus control sample c code is available in averlogic technologies, inc. upon request. the read/ write command format is as follows: write :

al44 0b AL440B november 28 , 2001 10 read :
following are the details: < s >: start signal scl sda high high high low the start signal is high to low transition on the sda line when scl is high. < write sa >: write slave address: 0h < read sa >: read slave address: 1h < register index >: value of the AL440B register index. < a >: acknowledge stage the acknowledge - related clock pulse is generated by the host (master). the host releases the sda line (high) for the AL440B (slave) to pull down the sda line during the acknowledge clock pulse. < na >: not acknowledged stage the acknowledge - related clock pulse is generated by the hos t (master). the host releases the sda line (high) during the acknowledge clock pulse, but the AL440B does not pull it down during this stage. < data >: data byte write to or read from the register index. in read operation, the host must release the sda lin e (high) before the first clock pulse is transmitted to the AL440B. < p >: stop signal scl sda high low high high the stop signal is low to high transition on the sda line when scl is high. suppose data f0h is to be written to register 0fh using write sla ve address 0h, the timing is as follows:
al44 0b AL440B november 28 , 2001 11 start slave addr = 0h ack ack ack stop index = 0fh data = f0h sda scl AL440B serial bus write timing suppose data is to be read from register 05h using read slave address 1h, the timing is as follows: start slave addr = 0h ack ack ack index = 05h read slave addr = 1h sda scl AL440B serial bus read timing nack stop data read cycle stop start 11.0 memory operation 11.1 power - on - reset & initia lization during the system power on, a 200 m s negative pulse on the /reset pin is required and will automatically initialize chip logic. apply a valid reset pulse to wrst and rrst after power - on - reset to reset read/write address pointer to zero. 11.2 wrst , rrst reset operation the reset signal can be given at any time regardless of the we, re and oe status, however, they still need to meet the setup time and hold time requirements with reference to the clock input. when the reset signal is provided during disabled cycles, the reset operation is not executed until cycles are enabled again. 11.3 control signals polarity select the AL440B provides the option for operating polarity on controlling signals. with this feature the application design can benefi t by matching up the operation polarity between AL440B and an existing interfacing devices without additional glue logic. the operating polarity of control signals we, re, wrst, rrst, ie, oe, irdy and ordy are controlled by /plrty signal. when /plrty is pulled high all 8 signals will be active low. when /plrty is pulled low all 8 signals will be active high.
al44 0b AL440B november 28 , 2001 12 11.4 fifo write operation in the fifo write operation, 8 bits of write data are input in synchronization with the wck clock. the fifo write operati on is determined by wrst, we, ie and wck signals and the combination of these signals could produce different write result. the /plrty signal determines the activated polarity of these control signals. the following tables describe the write functions un der different operating polarities. /plrty = vdd wrst we ie wck function l - - - write reset. the write pointer is reset to zero. h l l - normal write operation. h l h - write address pointer increases, but no new data will be written to memory. old data is retained in memory. (write mask function) h h - - write operation stopped. write address pointer is also stopped. /plrty = gnd wrst we ie wck function h - - - write reset. the write pointer is reset to zero. l h h - normal write operation. l h l - write address pointer increases, but no new data will be written to memory. old data is retained in memory. (write mask function) l l - - write operation stopped. write address pointer is also stopped. 11.5 fifo read operation in the fifo read o peration, 8 bits of read data are available in synchronization with the rck clock. the access time is stipulated from the rising edge of the rck clock. the fifo read operation is determined by rrst, re, oe and rck signals, so the combination of these sig nals could produce varying read results. the /plrty signal could decide the activated polarity of these control signals. the following tables describe the read functions under different operating polarities. /plrty = vdd rrst re oe rck function l l l - read reset. the read pointer is reset to zero. data in the address 0 is output. l l h - read reset. the read pointer is reset to zero. output is high impedance. l h l - read address pointer is stopped. output data is held. read address pointer will be reset to zero and data in the address 0 is output after re goes low.
al44 0b AL440B november 28 , 2001 13 l h h - read address pointer is stopped. output data is held. read address pointer will be reset to zero and output is high impedance after re goes low. h l l - normal read operati on. h l h - read address pointer increases. output is high impedance. (data skipping function) h h l - read address pointer is stopped. output data is held. h h h - read operation stopped. read address pointer is stopped. output is high impedance. /p lrty = gnd rrst re oe rck function h h h - read reset. the read pointer is reset to zero. data in the address 0 is output. h h l - read reset. the read pointer is reset to zero. output is high impedance. h l h - read address pointer is stopped. outpu t data is held. read address pointer will be reset to zero and data in the address 0 is output after re goes low. h l l - read address pointer is stopped. output data is held. read address pointer will be reset to zero and output is high impedance afte r re goes low. l h h - normal read operation. l h l - read address pointer increases. output is high impedance. (data skipping function) l l h - read address pointer is stopped. output data is held. l l l - read operation stopped. read address pointer is stopped. output is high impedance. when the new data is read, the read address should be between 192 and 524,287 cycles after the write address pointer, otherwise the output for new data is not guarantee. 11.6 irdy, ordy flags the irdy, ordy flags i ndicate the status of fifo. the irdy signal reports whether or not there is space available for writing new data to the fifo. an ordy signal reports whether or not there is valid new data available at output. the irdy and ordy signals only report the st atus of the address pointer; they will not stop or affect the read/write operations. the following tables describe the irdy/ordy functions under different operating polarities. /plrty = vdd signal state function h no more free space is available fo r new input data irdy l memory space is available for new input data. ordy h no new data is available in fifo memory.
al44 0b AL440B november 28 , 2001 14 l new data are available in the fifo memory. /plrty = gnd signal state function h memory space is available for new input dat a. irdy l no more free space is available for new input data h new data are available in the fifo memory. ordy l no new data is available in fifo memory. 11.7 window write register programming window data read/write is supported in the AL440B to benefit the designing effort for applications such as pip display. the window mode is enabled by driving low on /sdaen signal. a serial bus can program built - in registers to set up coordinates of the window and the settings take effect following by next read/wr ite reset pulse. window mirroring can cooperate with the window mode data access to flip window data in x or y direction. when window - mirroring function is turned on, write data can be stored in reverse sequence. the serial communication interface consi sts of 3 signals, they are scl (serial clock), sda (serial data) and /sdaen (window mode enable). the serial communication interface is enabled by driving low on /sdaen signal. the detail operation timing of the serial bus is illustrated in chapter 10. in window read/write mode, read and/or write may begin at the start address of any of the 8192 blocks. each block is 64 bytes in length. (8192 blocks x 64 byte = 512 kbytes) 8191 8190 8189 0 1 2 block number: 64 bytes each block memory size: 8192 blocks x 64 bytes = 512 kbytes AL440B window mode block address the window write related registers are listed as fol lows: wstart_l and wstart_h define the widow data write starting address. addr name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 02h wstart_l [7] [6] [5] [4] [3] [2] [1] [0] 03h wstart_h 0 0 0 [12] [11] [10] [9] [8] wstart (write start address) <= wstart_h[4 :0] & wstart_l ; wstart range is from 0 to 8191 (block).
al44 0b AL440B november 28 , 2001 15 wxsize_l and wxsize_h define the window data write horizontal size. addr name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 04h wxsize_l [7] [6] [5] [4] [3] [2] [1] [0] 05h wxsize_h 0 0 0 0 0 0 [9] [8 ] wxsize (write x size) <= wxsize_h[2:0] & wxsize_l ; wxsize range is from 0 to 1023 (block). wxstride_l and wxstride_h define the window data write horizontal width. addr name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 06h wstride_l [7] [6] [5] [4] [3] [ 2] [1] [0] 07h wstride_h 0 0 0 [12] [11] [10] [9] [8] wstride (write stride) <= wstride_h[4:0] & wstride _l ; wstride range is from ? 4096 to +4095 (block). when the value of wstride is negative, it is used to implement y - mirror function. wysize_l and wy size_h define the window data write vertical high. addr name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 08h wysize_l [7] [6] [5] [4] [3] [2] [1] [0] 09h wysize_h [15] [14] [13] [12] [11] [10] [9] [8] wysize (write y size) <= wysize_h & wysize_l ; write y size range is from 0 to 65535 (unsign). wwctrl is the register that control window data write function enable/disable and the window mirroring write. addr name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0ah wwctrl [7] [6] [5] 0 0 0 0 0 wwctrl[7] window wr ite mode enable 1: enable window write mode 0: disable window write mode. the memory is operating in standard fifo write mode. wwctrl[6] x - mirror function enable 1: enable x - mirror function 0: disable x - mirror function wwctrl[5] freeze function enable. t his function is as same as hardware ?write mask? function. when window write mode is enabled, software freeze function override hardware write mask function. on the other hand, in fifo mode (wwctrl[7] = ?0?), register wwctrl[5] is ignored. 1: enable softwa re freeze function 0: disable software freeze function a mirroring read/write function can be cooperated with the window - block data access function. by turning on the mirroring read/write function in the window block access mode, write data can be
al44 0b AL440B november 28 , 2001 16 stored in reversed sequence. for some applications like video conferencing, this function can correct reciprocal positioning of a captured object. please refer the following diagrams which illustrate window write operation. AL440B write window(1) wstart wstart+1xwstride wxsize wysize memory area wstart+2xwstride wstart+(wysize-1)x wstride wstart+(xsize-1) go back to wstart write window area normal write window: wwctrl[6]: 0 no x-mirror wstride: postive numer no y-mirror AL440B-03 write window(2) wstart wstart+1xwstride wxsize wysize memory area wstart+2xwstride wstart+(wysize-1)x wstride wstart-xsize+1 go back to wstart write window area x-mirror write window: wwctrl[6]: 1 x-mirror wstride: postive numer no y-mirror
al44 0b AL440B november 28 , 2001 17 AL440B write window(3) wstart wstart+1xwstride wxsize wysize memory area wstart+2xwstride wstart+(wysize-1)x wstride wstart-xsize+1 go back to wstart write window area x-mirror & y-mirror write window: wwctrl[6]: 1 x-mirror wstride: negative numer y-mirror 11.8 window read register programming the operations of window read function are same as window write. the operation of window read is operated independently from window write. the window read relat ed registers are listed as follows: rstart_l and rstart_h define the widow data read starting address. addr name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0bh rstart_l [7] [6] [5] [4] [3] [2] [1] [0] 0ch rstart_h 0 0 0 [12] [11] [10] [9] [8] rstart (read start address) <= rstart_h[4:0] & rstart_l ; rstart range is from 0 to 8191 (block). rxsize_l and rxsize_h define the window data read horizontal size. addr name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0dh rxsize_l [7] [6] [5] [4] [3] [2] [1] [0] 0eh rxsize_h 0 0 0 0 0 0 [9] [8] rxsize (read x size) <= rxsize_h[2:0] & rxsize_l ; wxsize range is from 0 to 1023 (block). rxstride_l and rxstride_h define the window data write horizontal width. addr name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0fh rstri de_l [7] [6] [5] [4] [3] [2] [1] [0] 10h rstride_h 0 0 0 0 [11] [10] [9] [8] rstride (read stride) <= rstride_h[3:0] & rstride _l ; rstride range is from 0 to +4095 (block).
al44 0b AL440B november 28 , 2001 18 rysize_l and rysize_h define the window data read vertical high. addr name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 11h rysize_l [7] [6] [5] [4] [3] [2] [1] [0] 12h rysize_h [15] [14] [13] [12] [11] [10] [9] [8] rysize (read y size) <= rysize_h & rysize_l ; write y size range is from 0 to 65535. rwctrl is the register that contro l window data read function enable/disable . addr name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 13h rwctrl [7] 0 0 0 0 0 0 0 rwctrl[7] read write mode enable 1: enable window read mode 0: disable window read mode. the memory is operating in standard fifo read mode. note: 1. x - mirror and y - mirror functions are not needed in window read mode, so they are not implemented in window read operation. 2. there is no ?freeze? function in window read mode. please refer to the following illustration as an application exa mple for the explanation of window read operation. AL440B read window rstart rstart+1xrstride rxsize rysize memory area rstart+2xrstride rstart+ (rysize-1)x rstride rstart+ (rxsize-1) go back to rstart read window area
al44 0b AL440B november 28 , 2001 19 12.0 electrical characteristics 12.1 absolute maximum ratings parameter rating unit v dd supply voltage - 0.3 ~ +3.8 v v p pin voltage - 0.3 ~ +(v dd +0.3) v i o output current - 20 ~ +20 ma t amb ambient op. temperature 0 ~ +85 c t stg storage temperature - 40 ~ +125 c 12.2 recommended operating conditions parameter min typ max unit v dd supply voltage +3.0 +3.3 +3.6 v v ih high level input voltage 0.7 v dd v dd v v il low le vel input voltage 0 0.3 v dd v 12.3 dc characteristics ( v dd = 3.3v, vss=0v. t amb = 0 to 70c) parameter min typ max unit i dd operating current - 52 62 ma i dds standby current - 14 - ma v oh hi - level output voltage 2.4 - v dd v v ol lo - level output vo ltage - - +0.4 v i li input leakage current (no pull - up or pull - down) - 5 - +5 m a i lo output leakage current (no pull - up or pull - down) - 5 - +5 m a r l input pull - up/pull - down resistance 50 k w 1. tested with outputs disabled (i out = 0) 2. rclk and wclk toggle a t 20 mhz and data inputs switch at 10 mhz.
al44 0b AL440B november 28 , 2001 20 12.4 ac characteristics ( v dd = 3.3v, vss=0v, t amb = 0 to 70c) 40mhz 80mhz parameter min max min max unit t wc wck cycle time 25 - 12.5 - ns t wph wck high pulse width 10 - 5 - ns t wpl wck low pulse width 10 - 5 - ns t rc rck cycle time 25 - 12.5 - ns t rph rck high pulse width 10 - 5 - ns t rpl rck low pulse width 10 - 5 - ns t ac access time - 20 - 12 ns t oh output hold time 6 - 4 - ns t hz output high - z setup time 5 4 ns t lz output low - z setup time 6 5 ns t wrs wrst setup time 8 - 4 - ns t wrh wrst hold time 8 - 5 - ns t rrs rrst setup time 8 - 4 - ns t rrh rrst hold time 8 - 5 - ns t ds input data setup time 5 - 4 - ns t dh input data hold time 6 - 5 - ns t wes we setup time 6 - 4 - ns t weh we ho ld time 6 - 5 - ns t wpw we pulse width 15 - 12 - ns t res re setup time 6 - 4 - ns t reh re hold time 6 - 5 - ns t rpw re pulse width 15 - 12 - ns t ies ie setup time 6 - 4 - ns t ieh ie hold time 6 - 5 - ns t ipw ie pulse width 15 - 12 - ns t oes oe setu p time 8 - 5 - ns t oeh oe hold time 8 - 5 - ns t opw oe pulse width 20 - 12 - ns t tr transition time 3 3 ns c i input capacitance - 7 - 7 pf
al44 0b AL440B november 28 , 2001 21 c o output capacitance - 7 - 7 pf the read address needs to be at least 192 cycles after the write address.
al44 0b AL440B november 28 , 2001 22 13.0 timing diagrams cycle n reset cycle (s) cycle 0 cycle 1 wck wrst di7~0 write cycle timing (write reset) t tr t wrs t wrh n-1 n 0 1 t ds t dh /plrty=vdd , we= "l" , ie= "l" cycle n cycle n+1 disable cycle (s) wck we di7~0 n-1 n t ds t dh write cycle timing (write enable) t wph t wpl t wes t weh t wc n+1 n+2 t wpw cycle n+2 /plrty=vdd ,ie="l" ,wrst="h"
al44 0b AL440B november 28 , 2001 23 cycle n cycle n+1 disable cycle (s) wck we di7~0 n-1 n t ds t dh write cycle timing (we, wrst) t wph t wpl t wes t weh t wc n+1 1 t wpw cycle 0 t wrs t wrh wrst 0 cycle 1 /plrty=vdd ,ie="l" cycle n cycle n+1 cycle n+3 wck ie di7~0 n-1 n write cycle timing (input enable) t wph t wpl t ies t ieh t wc n+1 t ipw t ih cycle n+2 cycle n+4 n+4 /plrty=vdd ,we="l" ,wrst="h"
al44 0b AL440B november 28 , 2001 24 rck rrst do7~0 n-1 n t oh read cycle timing (read reset) t rph t rpl 0 1 cycle n reset cycle (s) cycle 0 cycle 1 t rrs t rrh t ac 0 /plrty=vdd ,re= "l" ,oe= "l" cycle n cycle n+1 disable cycle (s) rck re do7~0 n-1 n read cycle timing (read enable) t rph t rpl t res t reh t rc n+1 t rpw t oh t ac n+2 cycle n+2 /plrty=vdd ,oe="l" ,rrst="h"
al44 0b AL440B november 28 , 2001 25 cycle n cycle n+1 cycle n+3 rck oe do7~0 n-1 n read cycle timing (output enable) t rph t rpl t oes t oeh t rc n+1 t opw t oh t ac cycle n+2 hi-z cycle n+4 n+4 t hz t lz /plrty=vdd ,re="l" ,rrst="h" cycle n cycle n+1 disable cycle (s) rck re do7~0 n-1 n read cycle timing (re, rrst) t rph t rpl t res t reh t rc n+1 t rpw t oh t ac 0 t rrs t rrh rrst cycle 0 /plrty=vdd ,oe="l"
al44 0b AL440B november 28 , 2001 26 cycle n reset cycle (s) cycle 0 cycle 1 wck wrst di7~0 write cycle timing (write reset) t tr t wrs t wrh n-1 n 0 1 t ds t dh /plrty=gnd , we= "h" , ie= "h" cycle n cycle n+1 disable cycle (s) wck we di7~0 n-1 n t ds t dh write cycle timing (write enable) t wph t wpl t wes t weh t wc n+1 n+2 t wpw cycle n+2 /plrty=gnd ,ie="h" ,wrst="l"
al44 0b AL440B november 28 , 2001 27 cycle n cycle n+1 disable cycle (s) wck we di7~0 n-1 n t ds t dh write cycle timing (we, wrst) t wph t wpl t wes t weh t wc n+1 1 t wpw cycle 0 t wrs t wrh wrst 0 cycle 1 /plrty=gnd ,ie="h" cycle n cycle n+1 cycle n+3 wck ie di7~0 n-1 n write cycle timing (input enable) t wph t wpl t ies t ieh t wc n+1 t ipw t ih cycle n+2 cycle n+4 n+4 /plrty=gnd ,we="h" ,wrst="l"
al44 0b AL440B november 28 , 2001 28 rck rrst do7~0 n-1 n t oh read cycle timing (read reset) t rph t rpl 0 1 cycle n reset cycle (s) cycle 0 cycle 1 t rrs t rrh t ac 0 /plrty=gnd ,re= "h" ,oe= "h" cycle n cycle n+1 disable cycle (s) rck re do7~0 n-1 n read cycle timing (read enable) t rph t rpl t res t reh t rc n+1 t rpw t oh t ac n+2 cycle n+2 /plrty=gnd ,oe="h" ,rrst="l"
al44 0b AL440B november 28 , 2001 29 cycle n cycle n+1 cycle n+3 rck oe do7~0 n-1 n read cycle timing (output enable) t rph t rpl t oes t oeh t rc n+1 t opw t oh t ac cycle n+2 hi-z cycle n+4 n+4 t hz t lz /plrty=gnd ,re="h" ,rrst="l" cycle n cycle n+1 disable cycle (s) rck re do7~0 n-1 n read cycle timing (re, rrst) t rph t rpl t res t reh t rc n+1 t rpw t oh t ac 0 t rrs t rrh rrst cycle 0 /plrty=gnd ,oe="h"
al44 0b AL440B november 28 , 2001 30 14.0 mechanical drawing ? 44 pin plastic tsop (ii)
AL440B november 28 , 2001 31 note: 1. controlling dimension : millimeters. 2. dimension ?d? does not include mold pr otrusion. mold protrusion shall not exceed 0.15(0.006?) per side. dimension ?e1? does not include interlead protrusion. interlead protrusion shall not exceed 0.25(0.01?) per side. 3. dimension ?b? does not include damar protrusions/intrusion. allowable dam ar protrusion shall not cause the lead to be wider than the max ?b? dimension by more than 0.13mm. damar intrusion shall not cause the lead to be narrower than the min ?b? dimension by more than 0.07mm. ?d ? ?b? (unit: mm)
AL440B november 28 , 2001 32 15.0 application notes 15.1 chip global reset reco mmend circuit to ensure a proper reset pulse can be applied to /reset pin (pin 27) to complete the power - on reset, the recommend reset circuit is to connect the AL440B /reset pin (pin 27) to v dd with a 2k w resistor and to ground with a 10 m f capacitor as f ollows. AL440B global reset circuit 8-bit input 8-bit output di[7:0] AL440B do[7:0] /reset 27 50k ohm 2k ohm 10 uf vdd it is also recommend adding buffers for the power - on reset circuit to increase the driving capability for any application with multiple AL440B chips. 15.2 the AL440B reference schematic we wck wrst re rrst ie irdy oe rck sda sdaen ordy scl favdd vdd3s vdd3s di0 di1 di2 di3 di4 di5 di6 di7 ctl0 ctl1 ctl2 ctl3 ctl4 do0 do1 do2 do3 do4 do5 do6 do7 ctl7 ctl8 ctl9 ctl10 ctl11 ctl12 ctl13 ctl14 vdd3s ctl5 vdd3s vdd3s fdvdd r1 2k + c67 10uf rnsmd1 10 8 1 7 6 2 5 3 4 rnsmd3 10 8 1 7 6 2 5 3 4 c55 0.1uf l5 fb 1 2 f b l7 fb 1 2 f b c62 0.1uf + c54 10uf r5 10 r2 2k c56 0.1uf c57 0.1uf r3 2k r5 10 r7 4.7k r6 4.7k rnsmd4 10 8 1 7 6 2 5 3 4 u8 al440 1 23 2 24 3 25 4 26 6 27 7 28 8 29 9 30 10 31 11 32 13 33 14 34 5 15 35 16 36 17 37 18 38 19 39 20 40 21 41 22 42 43 44 12 di0 sdaen di1 scl di2 sda di3 gnd di4 /reset di5 nc di6 vdd di7 ordy we rrst ie rck wck gnd wrst oe vdd irdy re plrty do7 test do6 avdd do5 nc do4 nc vdd nc do3 agnd do2 do1 do0 gnd populate r2 or r3 to select control singals polarity
contact information averlogic technologies, inc. 90 great oaks blvd. #204 san jose, ca 95119 usa tel : +1 408 361 - 0400 fax : +1 408 361 - 0404 e - mail : sales@averlogic.com url : www.averlogic.com averlogic tech nologies, corp. 4f., no.514, sec.2, cheng kung rd., nei - hu dist., taipei, taiwan r.o.c tel : +886 2 - 27915050 fax : +886 2 - 27912132 e - mail : sales@averlogic.com.tw url : www.averlogic.com.tw

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